Generally, semiconductor devices are electrical devices that utilize a semiconductor as a material component. Semiconductor devices are used in a variety of electronic applications, such as computers, cellular phones, personal computing devices, and many other applications. Home, industrial, and automotive devices that in the past comprised only mechanical components now have electronic parts that require semiconductor devices, for example.
Semiconductor devices are manufactured by depositing many different types of material layers over a semiconductor workpiece or wafer, and patterning the various material layers using lithography. The material layers typically comprise thin films of conductive, semiconductive, and insulating materials that are patterned and etched to form integrated circuits (IC's). There may be a plurality of transistors, memory devices, switches, conductive lines, diodes, capacitors, logic circuits, and other electronic components formed on a single die or chip.
Metallization layers are usually the top-most layers of semiconductor devices. The manufacturing of semiconductor devices is typically classified into two phases, the front end of line (FEOL) and the back end of line (BEOL). The BEOL is typically considered to be the point of the manufacturing process where metallization layers are formed, and the FEOL is considered to include the manufacturing processes prior to the formation of metallization layers.
While some integrated circuits have a single top layer of metallization, other integrated circuits comprise multi-level interconnects, wherein two or more metallization layers are formed over a semiconductor wafer or workpiece. Each conductive line layer typically comprises a plurality of conductive lines separated from one another by an insulating material, also referred to as an inter-level dielectric (ILD). The conductive lines in adjacent horizontal metallization layers may be connected vertically in predetermined places by vias formed between the conductive lines.
In the past, aluminum was used as a conductive line material in integrated circuits, which is easy to subtractively etch. As semiconductor devices are scaled down in size, there is a trend towards the use of copper for interconnect material, which is more conductive than aluminum. However, copper is difficult to subtractively etch, and thus, damascene processes are typically used to form copper conductive features.
In a damascene process, a material such as a dielectric is deposited over a wafer, and then the material is patterned with a conductive feature pattern. The conductive feature pattern typically comprises a plurality of trenches (for conductive lines), or apertures (for vias), for example. The trenches or apertures are then filled in with conductive material, and a chemical-mechanical polish (CMP) process and/or etch process is used to remove the excess conductive material from the top surface of the patterned material. The conductive material remaining within the patterned material comprises conductive features such as conductive lines and/or vias.
Damascene processes are typically either single or dual damascene. In a single damascene process, one metallization layer is formed at a time. In a dual damascene process, two adjacent horizontal layers are patterned, e.g., by forming two lithography patterns in two insulating material layers such as dielectric layers or in a single insulating material layer. The two patterns are then filled in with conductive material, and a CMP process is used to remove excess conductive material from over the insulating material layer, leaving patterned conductive material in the insulating material layers. For example, the patterns may comprise trenches for conductive lines in one insulating material layer portion and apertures for vias in the underlying insulating material layer portion. Thus, in a dual damascene process, conductor trenches and via apertures are filled in one fill step.
A prior art semiconductor device 100 comprising a single damascene structure is shown in FIG. 1 in a cross-sectional view and in FIG. 2 in a top view. A plurality of vias 106 is formed in a first insulating material layer 104 over a workpiece 102. The vias 106 may be formed in a single damascene process within the first insulating material layer 104, for example. A plurality of conductive features will be formed in a second insulating material layer 116 disposed over the first insulating material layer 104. To form the conductive features, a layer of resist 108 is deposited over the second insulating material layer 116, and the layer of resist 108 is patterned with a desired pattern for the conductive features. The layer of resist 108 is used as a mask to pattern the second insulating material layer 116, the layer of resist 108 is removed, and the second insulating material layer 116 is filled with a conductive material to form the conductive features. In a dual damascene process, the vias 106 are not filled prior to the patterning of the second insulating material layer 116, but rather, the vias 106 are formed simultaneously with the filling of the second insulating material layer 116 with conductive material.
In the structure shown, the conductive features to be formed in the second insulating material layer 116 comprise contact pads, which are rectangular or square, for example. The contact pads will be formed over and will make electrical contact to one or more of the vias 106, as shown. The pattern in the layer of resist 108 defines the shape of the conductive features.
A problem with the prior art structure and process shown and described with reference to FIGS. 1 and 2 is that the pattern in the layer of resist 108 comprises long, thin resist lines that are fragile and tend to be thinner at the bottom of the resist 108 proximate the via layer 104/106. The pattern in the layer of resist 108 has a high aspect ratio, e.g., about 3:1 or greater, for example. Thus, the resist 108 lines have a tendency to collapse.
To decrease the resist line collapse problem in the BEOL, sub-resolution assist features such as serifs and phase shifters are often used. Optical proximity correction (OPC) is used to generate the sub-resolution features on lithography masks. However, OPC is complex and time-consuming, and often does not completely prevent resist line collapse, particularly in resist line patterns that are very small and are relatively isolated from other features, and also when a negative focus is used for the lithography process, for example.